In a flat display panel, a gate driving circuit is generally used to provide a gate-on signal to gate electrodes of various thin film transistors at a pixel region. The gate driving circuit is formed on an array substrate of the flat display panel by using an array process, i.e., a gate driver on array (GOA) process. This process not only saves costs, but also allows the flat display panel to have a symmetric aesthetic design at two sides thereof. Meanwhile, wiring space for a bonding area and a fan-out area of a gate integrated circuit can also be eliminated, thereby achieving narrower border design.
The gate driving circuit is composed of cascaded shift registers. Each shift register is to provide a gate-on signal to a gate line connected with a signal outputting terminal of each shift register, so as to turn on a corresponding row of TFTs in the pixel region. Except for a first shift register, a signal outputting terminal of each of the rest of the shift registers is connected with the signal outputting terminal of a previous shift register. Each shift register includes a pulling-up node for controlling the signal outputting terminal to output the gate-on signal. When a potential of the pulling-up node is further pulled up, the signal outputting terminal outputs the gate-on signal.
Currently, a touch display panel is time-division driven in a display driving period and a touch driving period, that is, multiple touch control periods are inserted in a period of displaying one frame picture and each touch control period usually has a certain length of time duration. It is assumed that one touch control period begins after the signal output terminal of an n-th shift register has output a gate-on signal, the potential of the pulling-up node in a (n+1)-th shift register has changed to high potential. Since the time duration of each touch control period lasts longer, leakage may occur at the pulling-up node in the (n+1)-th shift register via a TFT connected with the pulling-up node during the time duration, and thus the potential of the pulling-up node in the (n+1)-th shift register may be decreased. When the touch control period ends and the (n+1)-th shift register starts to work, attenuation of the potential of the pulling-up node causes attenuation of a gate-on signal output from the signal outputting terminal of the (n+1)-th shift register, which may even result in that TFT in the pixel region cannot be turned on and thus cause an abnormal display of the touch display panel.